An electrically programmable nonvolatile memory, for example a flash memory or an electrically erasable programmable memory, has to dispose a pumping circuit beside the memory array thereof to provide the high voltages for programming and erasing the memory array. The programming or erasing voltage is several times of that provided by a power supply, and is related to the boosting stage number of the pumping circuit. On the other hand, writing more bits instead of one bit per one time will shorten the programming period and thereby speed up the programming procedure, so that the pumping circuit is also a large current apparatus. Due to the high voltage and large current, the pumping circuit occupies large chip area and needs high cost. However, the pumping circuit is available only for programming and erasing purpose, and as a result, it is not economical to employ a pumping circuit in each chip, especially for those devices with embedded programmable memory. In addition to the pumping circuit, some memory arrays are supplied with auxiliary circuits for programming and erasing procedure, for example the state machine in a flash memory to prevent the flash memory cells from over erasing, and these auxiliary circuits further expend chip area and manufacturing cost.
For a standard memory device, the memory capacity thereof is so huge that the area occupied by the memory array is quite large and thus the ratio of the area occupied by the pumping circuit and state machine is not too high. For other types of devices, nevertheless, such as microcontroller and digital signal processor (DSP), the memory capacity equipped thereof is not very large, and thus the ratio of the area occupied by the pumping circuit and state machine becomes much higher if these circuits are still kept to maintain a high programming efficiency. FIG. 1 is a diagram of a typical microcontroller 10, in which a central processing unit (CPU) 12 is connected to a static random access memory (SRAM) 14, an input/output (I/O) unit 15 and a multi-time programmable (MTP) memory 16. The MTP memory 16 is programmed with the program code for the operation of the CPU 12 and the data code for the apparatus the microcontroller 10 is applied thereto. To program the MTP memory 16, the programming voltages VPP and VNN are produced by the pumping circuit 18 from the supply voltage VDD and ground GND to the MTP memory 16. If the MTP memory 16 is implemented with flash memory cells, a state machine is further included together to prevent the MTP memory 16 from over erasing, and thereby the pumping circuit 18 and state machine 20 occupy large chip area. To reduce the chip area and cost, in U.S. Pat. No. 6,385,073 issued to Yu et al., the pumping circuit and common control circuit are separated from the individual chips and become shared circuits for a plurality of chips connected systematically and the individual chips only sustain the memory array and a reduced control circuit in each one.
Generally, after the microcontroller 10 is manufactured, the program code for the operation of the CPU 12 is programmed in the MTP memory 16 and will not altered unless the program code for the operation of the CPU 12 is updated with a new version. In contrast, the data code in the MTP memory 16 is updated depending on specific applications of the microcontroller 10. In other words, there is a need for the content of the MTP memory 16 to be conveniently updated in part. However, either a complete memory 22 embedded in the chip 10 or removal of the pumping circuit 18 and state machine 20 to reduce the chip area and cost, the chip 10 still cannot be on-system programmed by users themselves, since the program code for the operation of the CPU 12 is programmed in the MTP memory 16 and thereby the microcontroller 10 cannot program itself by directly programming the MTP memory 16.
For simplicity, the programmable nonvolatile memory hereinafter will refer to a complete memory except for the pumping circuit and state machine, or the memory array and its essential control circuit such as the decoder and sense amplifier. For the present invention not be indistinct, some details not concerned will be omitted in the description of various embodiments, without influencing illustrating and understanding the principle of the present invention. To distinguish the programmable nonvolatile memory referred in the present invention from conventional programmable nonvolatile memories, a dotted block 22 is additionally introduced in FIG. 1 to refer to a conventional programmable nonvolatile memory, such that readers can easily understand the embodiment designed in accordance with the principle and scope of the present invention.